1. Field of the Invention
The present invention relates to liquid crystal display devices, and more particularly, to a liquid crystal display device which is suitable for improving a picture quality by minimizing a Cgd variation in a liquid crystal panel even if there is a misalignment in the Y- or X-axis.
2. Background of the Related Art
To keep pace with development of the current information-oriented society, various improvements in display devices have been required. To meet these demands, various flat display devices, such as LCD (Liquid Crystal Display), PDP (Plasma Display Panel), ELD (Electro Luminescent Display), VFD (Vacuum Fluorescent Display), have been studied.
Of the various display devices, currently the LCD is used in a vast majority of mobile display devices owing to advantages that include good picture quality, light weight, thin, and low power consumption. The LCD has also been replacing the CRT (Cathode Ray Tube) in various applications. More particularly, besides the mobile display devices, such as monitors for notebook computers, the LCD has been developed as monitors for televisions for receiving, and displaying a broadcasting signal, and monitors for computers.
Despite of various technical developments for the LCD to serve as display devices in various fields, efforts for enhancing the picture quality as a kind of display device are contradictory to above advantages in many aspects.
Therefore, for using the LCD in various fields as general display devices, development of the LCD relies on the extent of realization of a high quality picture, such as high definition, high luminance, and large sized picture, while the features of light weight, thin, and low power consumption are maintained.
Such a LCD is provided with a liquid crystal panel for displaying a picture, and a driving part for applying a driving signal to the liquid crystal panel. The liquid crystal panel is provided with upper, and lower substrates bonded together with a space between the substrates, and a liquid crystal layer between the upper, and the lower substrates.
The lower substrate (a TFT array substrate) is provided with a plurality of gate lines arranged at regular intervals in one direction, a plurality of data lines arranged at regular intervals perpendicular to the gate lines, a plurality of pixel electrodes on every pixel region defined at every cross of the gate lines and the data lines in a form of matrix, and a plurality of thin film transistors (TFT) to be switched in response to a signal on the gate line for transmission of a signal on the data line to each pixel electrode.
On the upper substrate (a color filter substrate), there are a black matrix layer for shielding a light to parts excluding the pixel regions, R, B, G color filter layers for displaying colors, and a common electrode Vcom for displaying a picture.
The upper substrate and the lower substrate are bonded with sealant with a space between the substrates provided by means of spacers. The space is filled with the liquid crystal.
In fabrication of the LCD, rather than one liquid crystal panel being fabricated for each substrate, a plurality of liquid crystal panels are fabricated at the same time out of one large substrate. The number of liquid crystal panels depends on the size of the substrate and the size of the liquid crystal panel.
An equivalent circuit of a unit pixel on the lower substrate of the LCD will be described. FIG. 1 illustrates a related art equivalent circuit of a unit pixel in a TFT-LCD.
Referring to FIG. 1, the thin film transistor (TFT) has a drain electrode ‘d’ connected to an adjacent pixel electrode ‘P’, a gate electrode ‘g’ connected to a gate line ‘Gn’, and a source electrode ‘s’ connected to a data line Dm.
There is the liquid crystal between the pixel electrode ‘P’ and the common electrode Vcom. Parasitic capacitance Cgd is formed between the gate electrode ‘g’ and the drain electrode ‘d’ caused by misalignment, and the like. A liquid crystal capacitance Clc and storage capacitance act as a load that the TFT-LCD is required to drive.
The operation of the TFT-LCD will be described.
After applying a gate turn-on voltage to the gate electrode ‘g’ connected to a gate line ‘Gn’ intending to display, to make the TFT 10 conductive, a data voltage of a picture signal is applied to the source electrode ‘s’, so that the data voltage is provided to the drain electrode ‘d’.
According to this, the data voltage is provided both to the liquid crystal capacitance Clc and the storage capacitance through the pixel electrode ‘P’, to form an electric field dependent on a voltage difference between the pixel electrode and the common electrode Vcom.
In general, a plurality of the equivalent circuits in FIG. 1 are formed on the lower substrate of the LCD, and all the TFTs on the pixel regions have the same structures, and are oriented in the same direction. Therefore, even if a misalignment exists between layers, since all characteristics of the pixel regions (particularly, the parasitic capacitance Cgd caused by an overlapped area of the gate electrode and the drain electrode) are reduced or increased at the same time, there is no problem of picture quality drop caused by this.
However, the formation of the TFTs in the pixel regions in the same structures and orientation causes a problem of large power consumption. In order to reduce the power consumption, a technique is suggested in which the TFTs are formed, not in the same structures and orientation, but in a zigzag forms. A related art LCD in which the TFTs are arranged in a zigzag form will be described.
FIG. 2 illustrates a circuit of a TFT array of a related art LCD, FIG. 3 illustrates a layout of an LCD in FIG. 2, and FIG. 4 illustrates a layout when a misalignment occurs in a Y-axis direction in the layout of FIG. 3. At first, a related art TFT array circuit will be described.
Referring to FIG. 2, the related art TFT array circuit has a plurality of gate lines G1˜Gn arranged in one direction, a plurality of common lines Vcom 1˜Vcom n−1 arranged parallel to, and between the gate lines, a thin film transistor TFT at every crossing of the gate lines and the data lines having a gate electrode connected to the gate line, and a source electrode connected to the data line, and a liquid crystal capacitance capacitor Clc and storage capacitance capacitor Cst between the common line, and a drain electrode of the thin film transistor.
The TFTs are arranged such that pixel regions on the same horizontal line are driven by two adjacent gate lines, and pixel regions on the same vertical line are driven by one data line. That is, of pixel regions on the same horizontal line, odd numbered pixel regions are driven by an (n−1)th gate line Gn−1, and even numbered pixel regions are driven by an (n)th gate line Gn.
A layout of the foregoing related art TFT array will be described, taking adjacent gate lines and a TFT connected thereto as an example.
Referring to FIG. 3, the related art LCD is provided with first and second gate lines 30a and 30b arranged in one direction parallel to each other on a lower substrate, a common line 30c between, parallel to, and on the same layer with the first and second gate lines 30a and 30b, first and second data lines 34a and 34b arranged perpendicular to the first and second gate lines 30a and 30b to define first and second pixel regions, a first active layer 33a on the first gate line 30a adjacent to a right side of the first data line 34a, a first source electrode 35a of a ‘U’ form projected to a right side from the first data line 34a to overlap the first active layer 33a, a first drain electrode 36a arranged in a Y-axis direction opposite to, and spaced from the first source electrode 35a and overlapping the first active layer 33a, a first pixel electrode 37a on the first pixel region so as to be connected to the first drain electrode 36a through a first contact hole 38a, a second active layer 33b on the second gate line 30b adjacent to a right side of the second data line 34b, a second source electrode 35b of an inverted ‘U’ form projected to a right side from the second data line 34b to overlap the second active layer 33b, a second drain electrode 36b arranged in the Y-axis direction opposite to, and spaced from the source electrode 35b overlap the second active layer 33b, and a second pixel electrode 37b on the second pixel region so as to be connected to the second drain electrode 36b through the second contact hole 38b. 
The first pixel electrode 37a and the second pixel electrode 37b overlap the common line 30c form first and second storage capacitors in the first and second pixel regions, respectively.
The first and second gate lines under the first and second active layers 33a and 33b act as first and second gate electrodes, respectively, the first gate electrode, the first source electrode 35a, and the first drain electrode 36a form a first thin film transistor TFT1 in combination, and the second gate electrode, the second source electrode 35b, and the second drain electrode 36b form a second thin film transistor TFT2 in combination.
According to above structure, channel regions of the first and second thin film transistors TFT1, and TFT2 have ‘U’ forms, respectively.
Thus, pixel regions on the same horizontal line are driven by adjacent two gate lines, and pixel regions on the same vertical line are driven by one data line. According to this, the thin film transistors are arranged at upper, and lower sides of the same gate line in zigzag.
Referring to FIG. 4, if the TFTs are arranged such that pixel regions on the same horizontal line are driven by two adjacent gate lines, if misalignment occurs in the Y-axis direction, an overlapped area of the first gate electrode and the first drain electrode 36a of the first TFT1 and an overlapped area of the second gate electrode and the second drain electrode of the second TFT2 on the pixel region adjacent to the pixel region of the first TFT1 become different, and cause a difference in the Cgd.
In other words, as shown in FIG. 4, when the data lines 34a, and 34b, and the source/drain electrodes 35a, 35b, 36a, and 36b shift to a + direction of the Y-axis due to misalignment, since an overlap area (hatch part) of the first gate line 30a and the first drain electrode 36a becomes smaller, and an overlap area (hatch part) of the second gate line 30b and the second drain electrode 36b becomes larger, there is a difference of parasitic capacitances between gates and drains in adjacent pixel regions.
Next, a related art LCD will be described.
FIG. 5 illustrates a circuit of a TFT array of other related art LCD, FIG. 6 illustrates a layout of the LCD of FIG. 5, and FIG. 7 illustrates a layout when misalignment occurs in the layout of FIG. 6 in an X-axis direction.
Referring to FIG. 5, a TFT array circuit having applied to other related art LCD is provided with a plurality of gate lines G1˜Gn arranged in one direction, a plurality of common lines Vcom 1˜Vcom n arranged between, and parallel to the gate lines, a plurality of data lines D1˜Dm arranged perpendicular to the gate lines, and thin film transistors TFTs arranged at left and right sides of the data line in zigzag.
In this instance, the thin film transistors are arranged at left and right sides of the data line in zigzag so that pixel regions on the same horizontal line are driven by the same gate line, and pixel regions on the same vertical line are driven by adjacent two data lines. That is, two adjacent thin film transistors on the same vertical line are driven by different gate lines and different data lines, and connected to respective common lines to form first and second capacitors having a liquid crystal capacitance Clc and a storage capacitance Cst.
A layout of the foregoing related art TFT array will be described, taking two TFTs connected to a data line and adjacent tow gate lines as an example.
Referring to FIG. 6, the related art TFT array is provided with first and second gate lines 30a and 30b arranged in one direction parallel to each other on a lower substrate, a common line 30c between, parallel to, and one the same layer with the first and second gate lines 30a and 30b, a data line 34 arranged perpendicular to the first and second gate lines 30a and 30b to define pixel regions, a first gate electrode 32a projected to a left side of the data line 34 from one side of the first gate line 30a, a second gate electrode 32b projected to a right side of the data line 34 from one side of the second gate line 30b, first and second active layers 33a and 33b formed on the first and second gate electrodes 32a and 32b respectively, a first source electrode 35a of a ‘⊃’ form projected to a left side from the data line 34 to overlap the first active layer 33a, a first drain electrode 36a arranged in an X-axis direction (a direction parallel to the gate line) spaced from the first source electrode 35a and overlap the first active layer 33a, a first pixel electrode 37a on the pixel region connected to the first drain electrode 36a through a first contact hole 38a, a second source electrode 35b of a ‘⊂’ form projected to a right side from the data line 34 to overlap the second active layer 33b, a second drain electrode 36b arranged in the X-axis direction spaced from the second source electrode 35b and overlap the second active layer 33b, and a second pixel electrode 37b on the pixel region connected to the second drain electrode 36b through the second contact hole 38b. 
The pixel electrodes 37a and 37b overlap the common line 30c form storage capacitors, respectively.
The first gate electrode 32a, the first source electrode 35a, and the first drain electrode 36a form a first thin film transistor TFT1 in combination, the second gate electrode 32b, the second source electrode 35b, and the second drain electrode 36b form a second thin film transistor in combination. According to this, channel regions of the first and second thin film transistors have the ‘⊃’ and ‘⊂’ forms, respectively.
Referring to FIG. 7, when the TFTs are arranged at opposite sides of the data line, if the misalignment occurs in the X-axis direction, overlapped areas (hatched parts) of the gate electrode and the drain electrode on adjacent pixel regions differ, to cause a Cgd difference.
In other words, as shown in FIG. 7, in case the data line 34 and the source/drain electrodes 35a, 35b, 36a, and 36b shift in a ‘−’ direction of the X-axis direction due to misalignment, since an overlapped area (a hatched part) of the first gate electrode 32a and the second drain electrode 36a becomes small, and an overlapped area (a hatched part) of the second gate electrode 32b and the second drain electrode 36b becomes larger, a difference of the parasitic capacitances is formed between the gate and the drain on adjacent pixel regions.
Thus, the related art LCD having a structure shown in FIG. 3 or 4 has a Cgd difference between adjacent pixel regions when misalignment occurs in the Y- or X-axis direction, respectively, thereby decreasing the picture quality.